Code Generation

Figure 3.6 shows how the OVSF codes and scrambling codes are applied on the transmit
side and then used to decorrelate the signal energy of interest on the receive side,
having been processed through a root raised cosine (RRC) filter. Channels are selected
in the digital domain using a numerically controlled oscillator and a digital mixer.
Figure 3.7 shows steps in the uplink baseband generation. The DCCH is at a lower bit
rate than the DTCH to ensure a robust control channel. Segmentation and matching is
used to align the streams to a 10-ms frame structure. The composite signal is applied to
the I stream component and the DPCCH carrying the pilot, power control, and TFCI bits
with a spreading factor of 256 (providing good processing gain) applied to the Q stream.
The I and Q are coded with the scrambling code, and cross-coupled complex scrambling
takes place to generate HPSK.

Hybrid phase shift keying, also known as orthogonal complex quadrature phase shift
keying, allows handsets to transmit multiple channels at different amplitude levels
while still maintaining acceptable peak-to-average power ratios. This process uses
Walsh rotation, which effectively continuously rotates the modulation constellation to
reduce the peak to average (PAR) of the signal prior to modulation.
Figure 3.7 is taken from Agilent’s “Designing and Testing W-CDMA User Equipment”
Application Note 1356. To summarize the processing so far, we have performed
cyclic redundancy checking, forward error correction (FEC), interleaving, frame construction,
rate matching, multiplexing of traffic and control channels, OVSF code generation
and spreading, gain adjustment, spreading and multiplexing of the primary
control channel, scrambling code generation, and HPSK modulation.
The feedback coefficients needed to implement the codes are specified in the 3GPP1
standards, as follows:
 Downlink:
 38,400 chips of 218 Gold code
 512 different scrambling codes
 Grouped for efficient cell search
 Uplink:
 Long code: 38,400 chips of 225 Gold code
 Short code: 256 chips of very large Kasami code

An example hardware implementation might construct the function on a Xilinx Virtex
device—it uses approximately 0.02 percent of the device, compared with the 25 percent
required to implement an RRC/interpolator filter function. 70