Developing Microcontroller Architectures

Platform Software Solutions (Symbian/Java and Microsoft CE) is developing in parallel
with microcontroller architectures. The aim is to deliver better real-time performance
by improving memory management (hardware and software optimization) and
by supporting more flexible pipelining and multitasking. ARM 7 was a success in the
late 1990s because it took GSMs 100,000 lines of source code and made it run about six
times faster than the existing 8-bit microcontrollers being used.
A similar change in architecture will be needed, arguably, to support the highly
asynchronous multitasking requirements implicit in managing and multiplexing complex
multimedia (multiple per-user traffic streams). We are beginning to see similar
changes in DSP architecture (for example, the Siroyan example used in Chapter 5, on
handset hardware) and in memory architecture.
Software has an insatiable appetite for memory, and access delay is becoming an
increasingly important part of the delay budget. If you were to dissect a typical Random
Access Memory, you would find almost 60 percent of the die area and 90 percent
of the transistor count dedicated to memory access aids. Memory manufacturers are
beginning to include (yes, you have guessed already) integrated microprocessors—
sometimes known as Intelligent RAM, or IRAM). This means that:
 If you are a microcontroller manufacturer, you add DSP functionality and
memory to your product.
 If you are a DSP manufacturer, you add microcontroller and memory functionality
to your product.
 If you are a memory manufacturer, you add DSP and a microcontroller to your
product.
The software then struggles to adapt to these changing hardware form factors.
Access times are, of course, also a function of operating voltage. Flash memory
access times might vary between 70 and 100 ns depending on whether the device is
running at 1.8 or 2-5 V. High-speed (very power hungry) S-RAM can reduce access
delay to between 3 and 8 ns. A5-Volt flash memory might deliver 100 ns of access delay
running at 5 V, which could increase to 200 ns if reduced to 3 V. 224