Flexible Bandwidth Needs Flexible Hardware

As bandwidth becomes more bursty, hardware has to become more flexible. The success
of the ARM microcontroller has been the combination of the concept of a very long
instruction word and the variable-length instruction word�"the ability to change register
bit width.
In DSPs we have gradually begun to see the use of multiple multiply-accumulate
(MAC) units. This allows parallel and flexible processing to be performed, provided
the compiler has been designed sufficiently flexibly to take advantage of the multiplyaccumulate
functions. An example is the StarCore SC140. At 1.5 Volts the processor can
handle 1200 million multiply-accumulate functions per second, equivalent to 3000
RISC MIPs, assuming all four MAC blocks are fully utilized. The consumption of the
core, excluding peripherals, is 198 mW.
In these devices, typically two-thirds of the overall power requirement is created by
the drivers and interfaces. The more this functionality can be brought onto the chip, the
better the efficiency of the overall solution. However, this will tend to make the solution
less flexible in terms of the application footprint. It is sometimes hard to realize
flexibility and power consumption objectives.
Flexibility, along with the ability to parallel process, becomes a hardware quality
metric. Distributed DSP provides a good example of how to be flexible and parallel.
The same principle applies to memory, for example, the need for flexible lookup
tables when realizing filter structures. These filters are described as distributed arithmetic
filters and can deliver significant throughput and efficiency gains.
Summary
As content becomes more complex, channel processing becomes more complex. Complex
processing requires complex hardware.

As bandwidth becomes burstier, we have to provide more adaptive delivery bandwidth.
This requires adaptive hardware and, as we will see in the next chapter, adaptive
software. Adaptive hardware has costs: Designing RF power amplifiers and power supplies
to handle highly variable bit rates is quite tricky. Reconfigurable DSPs, variable bit
width microcontrollers, and reconfigurable memory add cost and complexity. We need
more expensive and exotic battery technologies to support high peak to mean power
requirements; bursty bandwidth is expensive bandwidth.
Most present reconfigurable components for example, FPGAs, reconfigurable DSPs,
and devices such as optical DSPs are not suitable for implementation in handsets
because of power budget and cost constraints. Application knowledge with these
devices is gained from their use initially in base stations (Node Bs). As power efficiency
improves and costs reduce, these techniques become applicable in handset designs. 151