Multiband Frequency Generation

Consider that the requirement is to design an architecture capable of generating discrete
frequencies across four frequency bands (a total of 995 × 200 kHz channels) at
duplex spacings of 45, 80, and 95 MHz while maintaining good frequency and phase
stability.
The system block used in cellular handsets (and prior generations of two-way
radios) to generate specific frequencies at specific channel spacings is the frequency
synthesizer—the process is described as frequency synthesis. PLLs have been the dominant
approach to RF frequency synthesis through 1G and 2G systems and will continue
to be the technology of choice for RF signal generation in 2.5G and 3G
applications.
The synthesizer is required to generate frequencies across the required range, increment
in channel sized steps, move rapidly from one channel to another (support frequency
hopping and handover), and have a low-noise, distortion-free output.
In 1G systems the network protocols allowed tens of milliseconds to shift between
channels—a simple task for the PLL. PLLs were traditionally implemented with relatively
simple integer dividers in the feedback loop. This approach requires that the
frequency/phase comparison frequency is equal to the minimum frequency step size
(channel spacing) required. This in turn primarily dictated the loop filter time constant—
that is, the PLL bandwidth and hence the settling time.
GSM has a channel spacing of 200 kHz, and so fREF is 200 kHz. But the GSM network
required channel changes in hundreds of microseconds. With a reference of 200 kHz
the channel switching rate cannot be met, so various speed-up techniques have been
developed to cheat the time constant during frequency changes.
In parallel with this requirement, PLL techniques have been developed to enable RF
signal generators and test synthesizers to obtain smaller step increments—without sacrificing
other performance parameters. This technique was based on the ability to
reconfigure the feedback divider to divide in sub-integer steps—the Fractional-N PLL.

This had the advantage of increasing the reference by a number equal to the fractional
division, for example:
Integer-N PLL
 O/P frequency = 932 MHz, fREF = 200 kHz
 N = 932 MHz/200 kHz = 4660
Fractional-N PLL
 If N can divide in 1/8ths, (that is, 0.125/0.250/0.375, etc.)
 O/P frequency = 932 MHz, fREF = 200 kHz × 8 = 1.6 MHz
 N = 932 MHz/1.6 MHz = 582.5
This should have two benefits:
 The noise generated by a PLL is primarily a function of the division ratio, so
reducing N should give a cleaner output, for example:
Integer-N PLL
 N = 4660
 Noise = 20log4660
 = 73.4 dB
Fractional-N PLL
 N= 582.5
 Noise = 20log582.5
 = 55 dB
for an 18.4-dB improvement.
 As the reference frequency is now 1.6 MHz, the loop is much faster and so
more easily meets the switching speed/settling time requirements. However,
the cost is a considerable increase in the amount of digital steering and compensation
logic that is required to enable the Fractional-N loop to perform. For
this reason, in many implementations the benefit has been marginal (or even
negative).
Interestingly, some vendors are again offering Integer-N loops for some of the more
advanced applications (for example, GPRS and EDGE) and proposing either two
loops—one changing and settling while the second is outputting—or using sophisticated
speed-up techniques.
A typical example has three PLLs on chip complete with VCO transistor and
varactors—resonators off chip. Two PLLs are for the 900 MHz and 1.8 GHz (PLL1) and
750 MHz to 1.5 GHz (PLL2). The third PLL is for the IF/demodulator function.

Summary
The introduction of GPRS has placed a number of new demands on handset designers.
Multislotting has made it hard to maintain the year-on-year performance improvements
that were delivered in the early years of GSM (performance improvements that
came partly from production volume—the closer control of RF component parameters).
This volume-related performance gain produced an average 1 dB per year of
additional sensitivity between 1992 and 1997.
Smaller form factor handsets, tri-band phones, and more recently, multislot GPRS
phones have together resulted in a decrease in handset sensitivity. In general, network
density today is sufficient to ensure that this is not greatly noticed by the subscriber but
does indicate that GSM (and related TDMA technologies) are nearing the end of their
maturation cycle in terms of technology capability. The room for improvement reduces
over time.
Present GPRS handsets typically support three or four time slots on the downlink
and one time slot on the uplink, to avoid problem of overheating and RF power budget
in the handset.
Good performance can still be achieved either by careful implementation of multiband-
friendly direct conversion receiver architectures or superhet designs with digital
IF processing. Handsets are typically dual-band (900/1800 MHz) or tri-band
(900/1800/1900 MHz).
In the next chapter, we set out to review the hardware evolution needed to deliver
third-generation handsets while maintaining backward compatibility with existing
GSM, GPRS, and EDGE designs.