Processor Cost and Processor Efficiency

Tables 4.10 and 4.11 show how the processor power budget has increased from 25 percent
of the overall power budget to 60 percent as we add image processing and high bandwidth displays and display drivers. This places substantial focus on processor
performance in terms of cost and power efficiency.
The general expectation in the mid to late 1990s was that a 3G phone would need
about three times the processor capacity of a 2G phone (300 rather than 100 MIPS). In
practice, first-iteration, third-generation handsets are absorbing between 800 and 1000
MIPS; that is, costs and power budgets are rather higher than planned. This is really
the consequence of user expectations moving on. The introduction of products like the
Palm Personal Digital Assistant (PDA) resulted in people expecting to have handwriting
recognition in portable products. Automotive guidance systems have resulted in
people expecting to have speech recognition in products. We expect to have simultaneous
voice and data, not either one or the other, and we expect video quality to be as
good as our home DVD system.
In addition, we are trying to offload many of the tasks previously done in the analog
domain down to baseband—that is, using DSPs to offload linearity problems and to
deliver low-cost filtering and waveform shaping.
In effect we are saying that a multimedia handset incurs substantial physical layer
and application layer processor overhead and substantial memory overhead. This
gives us a design challenge in terms of cost, product form factor and power budget.