QPSK Modulation

Channels are selected in the digital domain using a numerically controlled oscillator
(NCO) and digital mixers. Direct digital synthesis gives more precise frequency selection
and shorter settling time; it also provides good amplitude and phase balance. The
digital filter provides extremely linear phase and a very good shape factor. Figure 11.13
reminds us of the processing blocks.

W-CDMA requirements are as follows:
 Nyquist filter
 Root raised cosine filter: α = 0.22
 Sampling rate: 3.84 Msps × 4
 NCO
 60 MHz bandwidth for channel mapping
 High spurious free dynamic range (SFDR)
The highest rate processing function in the baseband transmitter is the pulse shaping
and vector modulation. These tasks must therefore be designed with care to minimize
processing overhead and hence power consumption and chip size. A design
example from Xilinx for a Node B unit employs an eight times oversampling approach.
(Sample rate is eight times symbol rate.) The output frequency for the channel is set
using a digital NCO (lookup table method).
The interpolation process is performed using the RRC filter as the first interpolator
filter, with a factor of eight sample rate increase. This is followed by two half-band factor
of two interpolators, fully exploiting the zero coefficient property of the half-band
filter design.
Because the sample rate at the input to the filters is already very high to accommodate
the 3.84 Mcps spread signal, the processing for all three filters is significant. With
a total of 3.87 billion MACs used for the I and Q channels, this task alone represents
about 38 times the processing load for a second-generation GSM phone.
The use of a digital IF design such as this is clearly not feasible for handset implementation
with current technology, since the power consumption of the DSP engines
would be too high. Even for Node B use, the approach is using approximately 25 percent
of a top-end Virtex 2 FPGA.